The present invention relates to semiconductor devices referred to as a so-called system in package, in which a plurality of semiconductor chips are mounted in one package form, and manufacturing methods thereof. The invention relates more particularly to a semiconductor device having a structure in which a semiconductor substrate is used to electrically coupling a plurality of semiconductor chips, and a manufacturing method thereof.
Recent trends of electronic apparatuses toward higher functions are requiring that semiconductor chips used in the apparatuses also have higher functions. However, an attempt to achieve higher functions with a system on chip (SoC) approach, in which a large-scale functional system is formed on one chip, requires large-scale development of the chip, causing problems of a long development period and high costs. Therefore, there have been proposed system in package (SiP) approaches, in which a plurality of semiconductor chips are mounted on an interposer substrate and the resultant component is used as one package part.
For example, Japanese Patent Laid-open No. 2004-79745 (hereinafter referred to as Patent Document 1) discloses an SiP approach in which plural chips are flip-chip mounted side-by-side on a silicon interposer substrate.
This SiP structure will be described with reference to FIG. 16. A silicon interposer substrate 53 has a surface interconnect layer 50 and through via portions 56. The surface interconnect layer 50 has fine interconnections (interconnections with e.g. submicron lines and spaces) for interconnection among plural chips, and pads with a small pitch (e.g. a pitch of 60 μm or smaller) for connection to the chips. The through via portion 56 is a conductive portion that is formed by e.g. plating in a manner of filling a through via that penetrates the silicon interposer substrate 53 in the thickness direction thereof, with an insulating film being interposed between the sidewall of the through via and the conductive portion. The through via portions 56 function to guide interconnections from the pads in the surface interconnect layer 50 to pads 49 that are formed (rearranged) on the lower surface (the opposite surface to the chip-mounted surface) of the silicon interposer substrate 53, and have a comparatively large pitch (e.g. a pitch of 100 μm or larger) allowing connection to an organic interposer substrate 57.
A plurality of semiconductor chips 2a and 2b are flip-chip connected via solder bumps 51 onto the surface interconnect layer 50 of the silicon interposer substrate 53, so as to be mounted on the silicon interposer substrate 53. The gap between the semiconductor chips 2a and 2b and the silicon interposer substrate 53 is filled with an underfill resin material 54.
The silicon interposer substrate 53 is electrically connected and mounted onto the organic interposer substrate 57 via the pads 49 provided on the lower surface, solder bumps 58, and lands 59 on the organic interposer substrate 57. The gap between the silicon interposer substrate 53 and the organic interposer substrate 57 is filled with an underfill resin material 55.
In addition, as another technique, Japanese Patent Laid-open No. Hei 8-250653 (hereinafter referred to as Patent Document 2) discloses a SiP approach employing a silicon interposer substrate that does not have through via portions. FIG. 17 illustrates the structure of this SiP. A plurality of semiconductor chips 62a and 62b are connected via solder bumps 64 to a silicon interposer substrate 61. The silicon interposer substrate 61 is connected via solder bumps 65 to an organic interposer substrate 63, through the same surface thereof as the surface on which the semiconductor chips 62a and 62b are mounted.